Using Cadence Virtuoso and TSMC's 65nm PDK, created a DAC which achieved ~20 MHz speed with less than 0.5 INL/DNL within simulation. The DAC was designed using a 3-MSB 5-LSB architecture.  This was my first ever tape-out experience and I learned a lot about designing and laying out chips. We presented our designs to Apple and I was one of six students awarded an Apple product for my work. 

Using Cadence Virtuoso and an IBM PDK, I designed a high speed, low power operational charge sharing DAC. The architecture for the DAC was taken from the "All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques -- Part II" paper by Suarez. The entire control logic was simulated using ideal logic gates for the charge splitting algorithm. I created a testbench to do transient sims and do a settling based INL/DNL test. Additionally, I further modified the topology to reduce parasitics generated from the switches.

Using Cadence Virtuoso and an IBM PDK, I designed a high speed, low power operational amplifier. This project was completed within the span of a week, so there was a heavy time crunch involved. The design was only tested across the nominal corner at normal temperatures. It consisted of a 2 stage double cascode with triode capacitor compensation to allow for tracking and consistent phase and gain margins.

Using Cadence Virtuoso GPDK045, I designed a switched capacitor amplifier converting my high speed operational amplifier into a 2-stage differential amplifier. I used two CMFB, one ideal for the first stage, and one non-ideal for the second stage. The design achieved the goal performance of 1/150th settling while being within 1.2 mW. The design was tested at 5 different process corners (FF, SF, FS, TT, and FF) at discrete temperature points of 0 °C, 27 °C, and 100 °C with a common mode voltage of -0.1V, 0V, and 0.1V.

Using Cadence Virtuoso GPDK045, I designed a high speed, low power operational amplifier. The design was tested with Monte Carlo simulation at 0 °C, 27 °C, and 100 °C; each of these temperatures was its own 1000 point run and achieved a yield of 90%, 91%, and 89%. The gain ranged from 1.3k to 1.8k, the UGF from 122 MHz to 220 MHz, power from 409uW to 601uW, and phase margin from  68 to 86.

Using Cadence Virtuoso GPDK045, I designed an open loop transimpedance amplifier with a bandwidth ranging from 77 MHz to 123 MHz, a gain ranging from 422 kΩ to 1.2 MΩ, and an input impedance ranging from 48Ω to 99Ω. The design was tested at 5 different process corners (FF, SF, FS, TT, and FF) at discrete temperature points of 0 °C, 27 °C, and 100 °C. 

For my MEMS class, we wrote a paper about how we would design and fabricate a MEMS Faraday cup. The overall shape of the design is based around the macro-level sized design, which allows more idealized characteristics. Attached is the paper.